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annotate src/init.s @ 119:a6a53e5c04bd

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Make a call stack implementation that is more complete and maybe cleaner.
author William Astle <lost@l-w.ca>
date Fri, 29 Dec 2023 01:40:39 -0700
parents 2d52cd154ed1
children c7f2f63cbcfe
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1 *pragmapush list
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2 *pragma list
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3 START orcc #0x50 ; make sure interrupts are disabled if we come here in an unusual way
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4 ifdef COCO3
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5 ldu #gime_inite ; point to end of GIME initializer
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6 ldx #GIME.INIT0+(gime_inite-gime_init) ; point to end of GIME registers
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7 ldb #gime_inite-gime_init ; number of bytes to transfer
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8 initc0 lda ,-u ; copy byte to GIME (count down so we init MMU before turning it on)
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9 sta ,-x
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10 decb ; done?
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11 bne initc0 ; brif not
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12 endc
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13 ldd #0xff34 ; initizer for below
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14 tfr a,dp ; set DP to I/O page
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15 setdp 0xff ; tell assembler about DP value
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16 clr PIA0.CA ; set PIA0 A to direction mode
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17 clr PIA0.CB ; set PIA0 B to direction mode
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18 clr PIA0.DA ; set PIA0 A to all inputs (comparator, keyboard rows)
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19 sta PIA0.DB ; set PIA0 B to all outputs (keyboard columns)
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20 stb PIA0.CA ; set PIA0 A to data mode, interrupt disabled, MUX to source 0
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21 stb PIA0.CB ; set PIA0 B to data mode, interrupt disabled, MUX to source 0
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22 clr PIA1.CA ; set PIA1 A to direction mode
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23 clr PIA1.CB ; set PIA1 B to direction mode
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24 deca ; set PIA1 A bits 7-1 output (DAC, RS232), 0 input (cassette)
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25 sta PIA1.DA
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26 lda #0xf8 ;* set PIA1 B bits 7-3 output (VDG stuff), 2-0 input (single bit sound,
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27 sta PIA1.DB ;* RS232 input, ram size input)
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28 stb PIA1.CA ; set PIA1 A to data mode, interrupt disabled, cassette motor off
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29 stb PIA1.CB ; set PIA1 B to data mode, interrupt disabled, sound off
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30 lda #2 ; set RS232 output to "marking" (stop bit)
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31 sta PIA1.DA
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32 lda #16 ; clear 16 SAM register bits
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33 ldu #SAMREG ; point to SAM register bits
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34 init0 sta ,u++ ; clear SAM bit
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35 deca ; done all?
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36 bne init0 ; brif not
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37 ; set the SAM to point to the text screen, which the code will handle at any
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38 ; arbitrary 512 byte aligned address in memory
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39 ifne (textscreen)&0x200
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40 sta SAM.F0SET
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41 endc
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42 ifne (textscreen)&0x400
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43 sta SAM.F1SET
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44 endc
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45 ifne (textscreen)&0x800
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46 sta SAM.F2SET
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47 endc
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48 ifne (textscreen)&0x1000
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49 sta SAM.F3SET
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50 endc
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51 ifne (textscreen)&0x2000
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52 sta SAM.F4SET
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53 endc
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54 ifne (textscreen)&0x4000
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55 sta SAM.F5SET
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56 endc
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57 ifne (textscreen)&0x8000
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58 sta SAM.F6SET
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59 endc
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60 ifdef COCO2B
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61 ; The following SAM configuration sequence is different from the one in the usual
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62 ; one used by the earlier models of the Coco because the Coco2B has the '785 variant
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63 ; of the SAM instead of the '783 variant. The '785 variant supports 16Kx4 RAMs which
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64 ; are used in Coco2B systems. Hence why there is a different version of this ROM
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65 ; just for the Coco2B.
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66 clr PIA0.DB ; strobe RAM size low
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67 ldb #4 ; is input low?
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68 bitb PIA1.DB
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69 beq init1 ; brif not
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70 sta SAM.M0SET ; program SAM for 16Kx4 RAMs
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71 sta SAM.P1SET
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72 skip2
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73 init1 sta SAM.M1SET ; program SAM for 64Kx1 RAMs
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74 else
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75 ifndef COCO3
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76 ; Detect the installed memory size so the SAM ('783 variant) can be correctly
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77 ; programmed for the installed memory. Note that this sequence is replaced with
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78 ; a different one for the Coco2B which has the '785 variant of the SAM.
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79 ldb #0xff ; strobe RAM size high
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80 stb PIA0.DB
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81 ldb #4 ; mask for ram size check
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82 bitb PIA1.DB ; is the bit set on ram size input?
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83 beq init2 ; brif not - 4Kx1 RAMs
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84 sta PIA0.DB ; clear RAM size output to see what happens (A is 0 from above)
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85 bitb PIA1.DB ; is it set now?
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86 beq init1 ; brif not - 64Kx1 RAMs
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87 leau -2,u ; adjust pointer so we set the other RAM size bit for the SAM (16Kx1)
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88 init1 sta -3,u ; set M0 (16Kx1) or M1 (64Kx1)
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89 endc
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90 endc
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91 init2 tfr a,dp ; set DP to bottom of memory (A is 0 from above)
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92 setdp 0 ; tell assembler about it
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93 lds #textscreen ; put the stack just below the text screen
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94 ifdef COCO3
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95 ; Check if we need to do a ROM/RAM copy, which will happen if the interrupt vectors are
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96 ; not flagged valid OR the reset vector isn't valid
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97 ldb INT.FLAG ; are the bounce vectors valid?
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98 cmpb #0x55
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99 bne initc4 ; brif not - do ROM/RAM copy
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100 ldb RSTFLG ; is reset vector valid?
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101 bne initc2 ; brif not - check secondary location
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102 ldx RSTVEC ; get reset vector
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103 ldb ,x ; is it valid?\
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104 cmpb #0x12
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105 bne initc2 ; brif not
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106 initc1 jmp ,x ; transfer control to warm start routine
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107 initc2 clr GIME.MMU0 ; check again with block 0 in the direct page
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108 ldb RSTFLG ; get new RSTFLG
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109 cmpb #0x55 ; valid?
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110 bne initc3 ; brif not
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111 ldx RSTVEC ; get new RSTVEC
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112 ldb ,x ; is it valid?
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113 cmpb #0x12
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114 beq initc1 ; brif so - transfer control
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115 initc3 ldb #0x38 ; restore MMU
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116 stb GIME.MMU0
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117 initc4 ldx #initc6 ; point to helper
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118 ldu #textscreen ; point to text screen
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119 ldb #initc7-initc6 ; bytes to copy
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120 initc5 lda ,x+ ; copy byte
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121 sta ,u+
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122 decb ; done?
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123 bne initc5 ; brif not
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124 ldu #0x8000 ; point to start of ROM
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125 jmp textscreen ; transfer control to helper in RAM
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126 initc6 sta SAM.TYCLR ; drop to ROM mode
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127 pulu d,x,y,s ; grab 8 bytes
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128 sta SAM.TYSET ; go to RAM mode
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129 pshu d,x,y,s ; stick the bytes in RAM
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130 leau 8,u ; move to next 8 bytes
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131 cmpu #0xfe00 ; end of stuff to copy?
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132 blo initc6 ; brif not
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133 jmp initc7 ; go back to mainline
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134 initc7 lds #textscreen ; reset stack to somewhere safe
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135 lda #0x12 ; activate ROM warm start handler
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136 sta warmstart
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137 ldx #INT.FLAG ; point to bounce vector destination
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138 ldu #int_init ; point to initializer for bounce vectors
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139 ldb #int_inite-int_init ; number of bytes to copy
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140 initc8 lda ,u+ ; copy byte
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141 sta ,x+
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142 decb ; done?
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143 bne initc8 ; brif not
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144 ; now recheck for warm start in case ROM/RAM copy made things valid
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145 endc
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146 ldb RSTFLG ; is the reset vector valid?
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147 cmpb #0x55
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148 bne coldstart ; brif not - do cold start
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149 ldx RSTVEC ; get warm start routine pointer
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150 ldb ,x ; does it start with NOP?
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151 cmpb #0x12
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152 bne coldstart ; brif not - do cold start
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153 jmp ,x ; transfer control to warm start routine
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154 ifdef COCO3
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155 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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156 ; GIME register initializer
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157 gime_init fcb GIME_COCO|GIME_MMUEN|GIME_FExx|GIME_SCS|GIME_ROMI32 ; enable MMU, SCS, constant page, internal ROM
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158 fcb GIME_TASK0 ; use MMU task 0
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159 fcb 0 ; do not enable IRQ sources
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160 fcb 0 ; do not enable FIRQ sources
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161 fdb 0xfff ; set timer to max value
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162 fdb 0 ; *reserved placeholder*
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163 fcb 0,0,0,0 ; SG4 screen settings with black border
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164 fcb 0x0f,0xe0,0x00,0x00 ; (puts screen in bottom 64K of memory)
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165 fcb 0x38,0x39,0x3a,0x3b ; MMU task 0 (bottom of top 64K of RAM)
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166 fcb 0x3c,0x3d,0x3e,0x3f ; (ROM shadow must be in 3c...3f)
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167 fcb 0x38,0x39,0x3a,0x3b ; MMU task 1 (copy of task 0)
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168 fcb 0x3c,0x3d,0x3e,0x3f
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169 fcb 18,54,9,36,63,27,45,38 ; palette values (RGB)
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170 fcb 0,18,0,63,0,18,0,38
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171 gime_inite equ *
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172 int_init fcb 0x55 ; vectors valid flag
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173 jmp SW3VEC ; bounce to stock ROM compatibility vector
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174 jmp SW2VEC ; bounce to stock ROM compatibility vector
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175 jmp FRQVEC ; bounce to stock ROM compatibility vector
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176 jmp IRQVEC ; bounce to stock ROM compatibility vector
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177 jmp SWIVEC ; bounce to stock ROM compatibility vector
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178 jmp NMIVEC ; bounce to stock ROM compatibility vector
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179 int_inite equ *
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180 endc
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181 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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182 ; Cold start handling
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183 coldstart ldx #dpstart ; point to start of direct page
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184 ldd #0 ; set up for blanking
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185 coldstart0 std ,x++ ; blank a couple of bytes
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186 cmpx #textscreen ; end of low memory?
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187 blo coldstart0 ; brif not
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188 ifndef COCO3
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189 ; This is the memory size detection sequence. This runs through memory starting at the bottom of memory
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190 ; and stops when it reaches something that can't be modified successfully. This is basically the same
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191 ; algorithm used by the stock ROM. It takes less space than doing a more pointed set of probes. The end
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192 ; result will be X pointing to the byte one below the top of RAM. This is intentional to ensure there
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193 ; is one writeable byte at the top of string space. Note that X will point to the byte after the end
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194 ; of the text screen when we get here.
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195 ldx #heapstart ; point to start of heap
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196 coldstart1 lda 2,x ; get original value at test location
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197 coma ; invert all bits
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198 sta 2,x ; write it to the memory location
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199 cmpa 2,x ; did it take?
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200 bne coldstart2 ; brif not
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201 com 2,x ; restore memory byte
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202 leax 1,x ; move pointer forward
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203 bra coldstart1 ; go check next byte
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204 else
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205 ; For the Coco3, we do not need to concern ourselves about where the top actual memory is so we don't
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206 ; bother doing a memory scan in the default 64K memory map. Because we always run from RAM, we can actually
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207 ; set the top of memory to the actual top of the 32K space without having to ensure there is an extra byte
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208 ; available above the string space.
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209 ldx #ROMSTART-1 ; point to top of memory
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210 endc
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211 coldstart2 stx memtop ; save absolute top of memory
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212 stx memsize ; save top of unreserved memory
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213 stx stringtab ; mark string space as empty
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214 leax -200,x ; allocate 200 bytes of string space
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215 stx freetop ; save top of free memory
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216 clr ,-x ; make a hole for the "end of call stack" flag
119
a6a53e5c04bd Make a call stack implementation that is more complete and maybe cleaner.
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217 stx cstackptr ; save the new call stack pointer
73
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218 leas ,x ; put the actual stack below the above
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219 ldx #heapstart ; point to start of free memory
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220 clr ,x+ ; put a NUL before the start of the program
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221 stx progtext ; put the start of the program there
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222 clr ,x+ ; put a NULL pointer to mark end of program
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223 clr ,x+
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224 stx vartab ; put start of integer variables at end of program
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225 stx objecttab ; also put the start of large objects there
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226 stx freestart ; mark the start of free memory
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227 lda #keyb_caps ; enable caps lock but disable all other shift states
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228 sta keyb_flags
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229 ldx #warmstart ; set up warm start handler
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230 stx RSTVEC
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231 lda #0x55 ; activate warm start handler
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232 sta RSTFLG
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233 ldd #0x7e3b ; opcodes for JMP extended and RTI
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234 ldx #irqhandler ; enable IRQ handler with a JMP at the vector
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235 sta IRQVEC
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236 stx IRQVEC+1
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237 sta FRQVEC ; initialize FIRQ handler with JMP
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238 ldx #firqhandler
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239 stx FRQVEC+1
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240 stb NMIVEC ; initialize NMI to RTI
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241 stb SW3VEC ; initialize SWI3 to RTI
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242 stb SW2VEC ; initialize SWI2 to RTI
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243 stb SWIVEC ; initialize SWI to RTI
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244 ldx #greeting ; display greeting
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245 jsr console_outstr
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246 bra warmstartb ; finish up initialization
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247 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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248 ; Warm start handling
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249 ifdef COCO3
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250 warmstart fcb 0xff ; set to 0xff to force ROM/RAM copy on reset
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251 else
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252 warmstart nop ; flag warm start routine as valid
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253 endc
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254 jsr console_clear ; clear screen
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255 clr filenum ; reset I/O channel to the screen
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256 warmstartb jsr keyb_reset ; reset the keyboard
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257 lda #0x35 ; enable VSYNC interrupt in PIA
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258 sta PIA0.CB
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259 andcc #0xaf ; enable interrupts at the cpu
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260 jmp immediate ; go start immediate mode
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261 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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262 ; System startup message
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263 ; (start with form feed to clear screen; saves 2 bytes over 'jsr console_clear' in cold start)
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264 greeting fcc '\fLWBASIC VERSION 2022.0\r\n'
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265 fcc 'COPYRIGHT (C) 2022 BY LOST\r\n'
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266 fcc 'WIZARD ENTERPRISES INC.\r\n'
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267 fcn '\n'
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268 *pragmapop list