Mercurial > hg > index.cgi
diff src/defs.s @ 73:2d52cd154ed1
Split some code into separate files for easier management
Because the source for lwbasic is so large, split it into several
different files to make it easier to navigate and modify. This is
part one of the split.
| author | William Astle <lost@l-w.ca> |
|---|---|
| date | Sun, 06 Aug 2023 00:12:29 -0600 |
| parents | |
| children | ba559f231929 |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/defs.s Sun Aug 06 00:12:29 2023 -0600 @@ -0,0 +1,208 @@ + *pragmapush list + *pragma list +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Various constants +console_curdel equ 10 ; delay between cursor blink cycles +keyb_bufflen equ 64 ; keyboard ring buffer length +keyb_repdeli equ 40 ; ticks before initial repeat (2/3 s) +keyb_repdelr equ 6 ; 10 repeats per second +keyb_caps equ 0x80 ; capslock enabled +keyb_alt equ 0x04 ; alt pressed +keyb_ctrl equ 0x02 ; ctrl pressed +keyb_shift equ 0x01 ; shift pressed +linebuffsize equ 0x100 ; the line input buffer (256 bytes) +stringstacknum equ 20 ; number of entries on the anonymous string descriptor stack +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Data structure used for calculations. Calculations are handled via structurs called value accumulators. A value +; accumulator consists of a data type flag (at the end of the structure) and a data area whose layout varies based +; on the actual data type. The layouts for each value type are described below. +; +; A value type that is NULL (not set to anything) has type 0 (valtype_none) and the rest should be zero. +; +; A value accumulator has the following structure for floating point: +; Offset Length Contents +; 0 1 fp exponent +; 1 4 fp mantissa +; 5 1 fp sign +; 6 1 value type +; +; A value accumulator has the following structure for integers: +; Offset Length Contents +; 0 1 *unsued* +; 1 4 integer value (two's complement) +; 5 1 *unused* +; 6 1 value type +; +; A value accumulator has the following structure for a string: +; Offset Length Contents +; 0 2 string length +; 2 2 *reserved for string data pointer expansion, must be zero* +; 4 2 string data pointer +; 6 1 value type +; +; Value type constants +valtype_none equ 0 ; unknown value type +valtype_int equ 1 ; integer (32 bit) value (signed) +valtype_float equ 2 ; float type (40 bit) value +valtype_string equ 3 ; string type (16 bit length, 16(32) bit data pointer +; Value accumulator structure definitions +val.type equ 6 ; value type offset +val.fpexp equ 0 ; fp exponent offset +val.fpmant equ 1 ; fp mantissa offset +val.fpsign equ 5 ; fp sign offset +val.int equ 1 ; integer offset +val.strlen equ 0 ; string length offset +val.strptr equ 4 ; string data pointer (low word) +val.size equ 7 ; size of a value accumulator +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ifdef COCO3 +; GIME INIT0 +GIME_COCO equ 0x80 ; Set for coco2 compatible mode (video display) +GIME_MMUEN equ 0x40 ; Set to enable MMU +GIME_IEN equ 0x20 ; GIME IRQ enable +GIME_FEN equ 0x10 ; GIME FIRQ enable +GIME_FExx equ 0x08 ; Enable constant RAM at 0xFExx (comes from block 0x3f) +GIME_SCS equ 0x04 ; Set to enable standard SCS (switches 0xFF5x) +GIME_ROME16 equ 0x00 ; 16K internal, 16K external ROM mode +GIME_ROME32 equ 0x03 ; 32K external ROM +GIME_ROMI32 equ 0x02 ; 32K internal ROM +; GIME INIT1 +GIME_TMRFAT equ 0x20 ; TIMER ticks approx every 279.365 ns +GIME_TMRSLOW equ 0x00 ; TIMER ticks approx every 63.695 µs +GIME_TASK0 equ 0x00 ; MMU task 0 +GIME_TASK1 equ 0x01 ; MMU task 1 +; GIME interrupt enable/status bits +GIME_ITIMER equ 0x20 ; TIMER interrupt (timer reaches 0) +GIME_IHBORD equ 0x10 ; HSYNC interrupt (falling edge) +GIME_IVBORD equ 0x08 ; VSYNC interrupt (falling edge) +GIME_ISERIAL equ 0x04 ; Falling edge of signal on pin 4 of serial port +GIME_IKEYBOARD equ 0x02 ; Interrupt if a 0 bit appears on bits 6-0 of PIA0.DA +GIME_ICART equ 0x01 ; Interrupt on falling edge of pin 8 of cartridge port +; GIME VMODE +GIME_BP equ 0x80 ; enable bit plane mode +GIME_BPI equ 0x20 ; colour burst phase inversion (composite output only) +GIME_MONO equ 0x10 ; disable colour burst (composite output only) +GIME_H50 equ 0x08 ; set to 50Hz operation +GIME_LPR1 equ 0x00 ; one line per row +GIME_LPR2 equ 0x02 ; two lines per row (also works on graphics) +GIME_LPR8 equ 0x03 ; 8 lines per row +GIME_LPR9 equ 0x04 ; 9 lines per row +GIME_LPR10 equ 0x05 ; 10 lines per row +GIME_LPR11 equ 0x06 ; 11 lines per row +GIME_LPRINF equ 0x07 ; "infinite" lines per row +; GIME VRES +GIME_LPF192 equ 0x00 ; 192 lines on screen +GIME_LPF200 equ 0x40 ; 200 lines on screen (actually 199 due to hardware bug) +GIME_LPF225 equ 0x60 ; 225 lines on screen +GIME_BPR16 equ 0x00 ; 16 bytes per row +GIME_BPR20 equ 0x04 ; 20 bytes per row +GIME_BPR32 equ 0x08 ; 32 bytes per row +GIME_BPR40 equ 0x0c ; 40 bytes per row +GIME_BPR64 equ 0x10 ; 64 bytes per row +GIME_BPR80 equ 0x14 ; 80 bytes per row +GIME_BPR128 equ 0x18 ; 128 bytes per row +GIME_BPR160 equ 0x1c ; 160 bytes per row +GIME_TXT32 equ 0x00 ; 32 characters per row +GIME_TXT40 equ 0x04 ; 40 characters per row +GIME_TXT64 equ 0x10 ; 64 characters per row +GIME_TXT80 equ 0x14 ; 80 characters per row +GIME_BPP1 equ 0x00 ; 1 bit per pixel +GIME_BPP2 equ 0x01 ; 2 bits per pixel +GIME_BPP4 equ 0x02 ; 4 bits per pixel +GIME_TXTATTR equ 0x01 ; text attributes enabled + endc + ifdef COCO3 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Stuff on the fixed memory page + org 0xfe00 + rmb 0xed ; unused +INT.FLAG rmb 1 ; validity flag +INT.SWI3 rmb 3 ; SWI3 bounce vector +INT.SWI2 rmb 3 ; SWI2 bounce vector +INT.FIRQ rmb 3 ; FIRQ bounce vector +INT.IRQ rmb 3 ; IRQ bounce vector +INT.SWI rmb 3 ; SWI bounce vector +INT.NMI rmb 3 ; NMI bounce vector + endc +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Hardware definitions for the I/O page + org 0xff00 +PIA0 equ * ; Keyboard PIA +PIA0.DA rmb 1 ; PIA0 data/direction A +PIA0.CA rmb 1 ; PIA0 control A +PIA0.DB rmb 1 ; PIA0 data/direction B +PIA0.CB rmb 1 ; PIA0 control B + rmb 28 ; mirror images of PIA0 +PIA1 equ * ; DA/misc stuff +PIA1.DA rmb 1 ; PIA1 data/direction A +PIA1.CA rmb 1 ; PIA1 control A +PIA1.DB rmb 1 ; PIA1 data/direction B +PIA1.CB rmb 1 ; PIA1 control B + rmb 28 ; mirror images of PIA1 + rmb 16 ; SCS/Disk controller + rmb 16 ; second half of SCS area + rmb 32 ; miscelaneous hardware + ifdef COCO3 + rmb 16 ; *reserved* (unused but the GIME drives them) +GIME.INIT0 rmb 1 ; basic GIME system config +GIME.INIT1 rmb 1 ; MMU task and timer rate +GIME.IRQ rmb 1 ; GIME IRQ enable/status register +GIME.FIRQ rmb 1 ; GIME FIRQ enable/status register +GIME.TIMER rmb 2 ; GIME programmable timer + rmb 2 ; *reserved* +GIME.VMODE rmb 1 ; GIME video mode setting +GIME.VRES rmb 1 ; GIME video resolution setting + rmb 1 ; *reserved* (used for MMU expansion on some memory boards) +GIME.BORDER rmb 1 ; GIME border colour +GIME.VSCROLL rmb 1 ; vertical scroll offset register/VDG screen mode variation +GIME.VOFFSET rmb 2 ; address of video memory (8 byte increments) +GIME.HOFFSET rmb 1 ; horizontal scroll offset +GIME.MMU equ * ; MMU registers (two tasks) +GIME.MMU0 rmb 8 ; MMU task 0 +GIME.MMU1 rmb 8 ; MMU task 1 +GIME.PALETTE rmb 16 ; Palette registers + else + rmb 64 ; unused on Coco 1/2 (GIME on Coco 3) + endc +SAMREG equ * ; the SAM configuration register +SAM.V0CLR rmb 1 ; SAM video mode bits +SAM.V0SET rmb 1 +SAM.V1CLR rmb 1 +SAM.V1SET rmb 1 +SAM.V2CLR rmb 1 +SAM.V2SET rmb 1 +SAM.F0CLR rmb 1 ; SAM screen address bits +SAM.F0SET rmb 1 +SAM.F1CLR rmb 1 +SAM.F1SET rmb 1 +SAM.F2CLR rmb 1 +SAM.F2SET rmb 1 +SAM.F3CLR rmb 1 +SAM.F3SET rmb 1 +SAM.F4CLR rmb 1 +SAM.F4SET rmb 1 +SAM.F5CLR rmb 1 +SAM.F5SET rmb 1 +SAM.F6CLR rmb 1 +SAM.F6SET rmb 1 +SAM.P1CLR rmb 1 ; SAM "page 1" selection (or extra memory type flag) +SAM.P1SET rmb 1 +SAM.R0CLR rmb 1 ; SAM R0 bit (address dependent speedup, not used on Coco3) +SAM.R0SET rmb 1 +SAM.R1CLR rmb 1 ; SAM R1 bit (full speedup/coco 3 speedup) +SAM.R1SET rmb 1 +SAM.M0CLR rmb 1 ; SAM M0/M1 bits (memory type, not used on Coco3) +SAM.M0SET rmb 1 +SAM.M1CLR rmb 1 +SAM.M1SET rmb 1 +SAM.TYCLR rmb 1 ; force ROM mode (map type 0) +SAM.TYSET rmb 1 ; set RAM mode (map type 1) + rmb 18 ; *MPU reserved* +CPU.SWI3 rmb 2 ; CPU SWI3 vector +CPU.SWI2 rmb 2 ; CPU SWI2 vector +CPU.FIRQ rmb 2 ; CPU FIRQ vector +CPU.IRQ rmb 2 ; CPU IRQ vector +CPU.SWI rmb 2 ; CPU SWI vector +CPU.NMI rmb 2 ; CPU NMI vector +CPU.RESET rmb 2 ; CPU RESET/startup vector + *pragmapop list