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changeset 5:80c18925436d
More Coco3 specific initialization and interrupt vectors
Set up interrupt vectors, both Coco3 and Coco1/2 vectors and also implement
ROM/RAM copy for the Coco3. The warm start detection is also compatible with
the stock ROM.
| author | William Astle <lost@l-w.ca> |
|---|---|
| date | Fri, 04 Nov 2022 00:29:38 -0600 |
| parents | 2b6e6b827bd7 |
| children | 80b9b4503bb4 |
| files | src/lwbasic.s |
| diffstat | 1 files changed, 91 insertions(+), 14 deletions(-) [+] |
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--- a/src/lwbasic.s Thu Nov 03 22:27:06 2022 -0600 +++ b/src/lwbasic.s Fri Nov 04 00:29:38 2022 -0600 @@ -86,6 +86,19 @@ GIME_BPP4 equ 0x02 ; 4 bits per pixel GIME_TXTATTR equ 0x01 ; text attributes enabled endc + ifdef COCO3 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Stuff on the fixed memory page + org 0xfe00 + rmb 0xed ; unused +INT.FLAG rmb 1 ; validity flag +INT.SWI3 rmb 3 ; SWI3 bounce vector +INT.SWI2 rmb 3 ; SWI2 bounce vector +INT.FIRQ rmb 3 ; FIRQ bounce vector +INT.IRQ rmb 3 ; IRQ bounce vector +INT.SWI rmb 3 ; SWI bounce vector +INT.NMI rmb 3 ; NMI bounce vector + endc ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Hardware definitions for the I/O page org 0xff00 @@ -174,7 +187,13 @@ RSTFLG rmb 1 ; 0x55 if RSTVEC is valid RSTVEC rmb 2 ; points to warm start routine (must start with NOP) rmb 0x100-* ; make sure the stuff that isn't direct page is outside of it - rmb 0x100 ; non direct page stuff +SW3VEC rmb 3 ; SWI3 vector (for compatibility) +SW2VEC rmb 3 ; SWI2 vector (for compatibility) +SWIVEC rmb 3 ; SWI vector (for compatibility) +NMIVEC rmb 3 ; NMI vector (for compatibility) +IRQVEC rmb 3 ; IRQ vector (for compatibility) +FRQVEC rmb 3 ; FIRQ vector (for compatibility) + rmb 0xee ; unused textscreen rmb 0x200 ; the actual text screen (must be on 512 byte alignment) org 0x8000 ; the hardware puts the ROMs here; it's not negotiable START orcc #0x50 ; make sure interrupts are disabled if we come here in an unusual way @@ -268,6 +287,56 @@ init2 tfr a,dp ; set DP to bottom of memory (A is 0 from above) setdp 0 ; tell assembler about it lds #textscreen ; put the stack just below the text screen + ifdef COCO3 +; Check if we need to do a ROM/RAM copy, which will happen if the interrupt vectors are +; not flagged valid OR the reset vector isn't valid + ldb INT.FLAG ; are the bounce vectors valid? + cmpb #0x55 + bne initc4 ; brif not - do ROM/RAM copy + ldb RSTFLG ; is reset vector valid? + bne initc2 ; brif not - check secondary location + ldx RSTVEC ; get reset vector + ldb ,x ; is it valid?\ + cmpb #0x12 + bne initc2 ; brif not +initc1 jmp ,x ; transfer control to warm start routine +initc2 clr GIME.MMU0 ; check again with block 0 in the direct page + ldb RSTFLG ; get new RSTFLG + cmpb #0x55 ; valid? + bne initc3 ; brif not + ldx RSTVEC ; get new RSTVEC + ldb ,x ; is it valid? + cmpb #0x12 + beq initc1 ; brif so - transfer control +initc3 ldb #0x38 ; restore MMU + stb GIME.MMU0 +initc4 ldx #initc6 ; point to helper + ldu #textscreen ; point to text screen + ldb #initc7-initc6 ; bytes to copy +initc5 lda ,x+ ; copy byte + sta ,u+ + decb ; done? + bne initc5 ; brif not + ldu #0x8000 ; point to start of ROM + jmp textscreen ; transfer control to helper in RAM +initc6 sta SAM.TYCLR ; drop to ROM mode + pulu d,x,y,s ; grab 8 bytes + sta SAM.TYSET ; go to RAM mode + pshu d,x,y,s ; stick the bytes in RAM + leau 8,u ; move to next 8 bytes + cmpu #0xfe00 ; end of stuff to copy? + blo initc6 ; brif not + jmp initc7 ; go back to mainline +initc7 lds #textscreen ; reset stack to somewhere safe + ldx #INT.FLAG ; point to bounce vector destination + ldu #int_init ; point to initializer for bounce vectors + ldb #int_inite-int_init ; number of bytes to copy +initc8 lda ,u+ ; copy byte + sta ,x+ + decb ; done? + bne initc8 ; brif not +; now recheck for warm start in case ROM/RAM copy made things valid + endc ldb RSTFLG ; is the reset vector valid? cmpb #0x55 bne coldstart ; brif not - do cold start @@ -294,29 +363,37 @@ fcb 18,54,9,36,63,27,45,38 ; palette values (RGB) fcb 0,18,0,63,0,18,0,38 gime_inite equ * +int_init fcb 0x55 ; vectors valid flag + jmp SW3VEC ; bounce to stock ROM compatibility vector + jmp SW2VEC ; bounce to stock ROM compatibility vector + jmp FRQVEC ; bounce to stock ROM compatibility vector + jmp IRQVEC ; bounce to stock ROM compatibility vector + jmp SWIVEC ; bounce to stock ROM compatibility vector + jmp NMIVEC ; bounce to stock ROM compatibility vector +int_inite equ * endc ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Cold start handling -coldstart +coldstart ifndef COCO3 ; Need to ensure the vectors are at 0xbff2 zmb 0xbff2-* ; pad ROM up to the vector point - fdb 0 ; SWI3 vector - fdb 0 ; SWI2 vector - fdb 0 ; FIRQ vector - fdb 0 ; IRQ vector - fdb 0 ; SWI vector - fdb 0 ; NMI vector + fdb SW3VEC ; SWI3 vector + fdb SW2VEC ; SWI2 vector + fdb FRQVEC ; FIRQ vector + fdb IRQVEC ; IRQ vector + fdb SWIVEC ; SWI vector + fdb NMIVEC ; NMI vector fdb START ; RESET vector (ROM entry point) endc ifdef COCO3 zmb 0xfff2-* ; pad ROM to bottom of vectors - fdb 0 ; SWI3 vector - fdb 0 ; SWI2 vector - fdb 0 ; FIRQ vector - fdb 0 ; IRQ vector - fdb 0 ; SWI vector - fdb 0 ; NMI vector + fdb INT.SWI3 ; SWI3 vector + fdb INT.SWI2 ; SWI2 vector + fdb INT.FIRQ ; FIRQ vector + fdb INT.IRQ ; IRQ vector + fdb INT.SWI ; SWI vector + fdb INT.NMI ; NMI vector fdb START ; RESET vector (ROM entry point) else zmb 0x10000-* ; pad ROM to full size