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changeset 2:19eac734a518
Makefile to actually build something with initial start to ROM init code
| author | William Astle <lost@l-w.ca> |
|---|---|
| date | Thu, 03 Nov 2022 21:18:51 -0600 |
| parents | a5a4c575a2c8 |
| children | 05ef3a3b6d65 |
| files | Makefile src/lwbasic.s |
| diffstat | 2 files changed, 194 insertions(+), 0 deletions(-) [+] |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Makefile Thu Nov 03 21:18:51 2022 -0600 @@ -0,0 +1,47 @@ +.PHONY: all +all: bin/lwbasic.rom bin/lwbasic-coco2b.rom bin/lwbasic-coco3.rom bin/coco2.zip bin/coco2b.zip bin/coco3.zip + +bin/lwbasic.rom: src/lwbasic.s + lwasm --raw --list=src/lwbasic.list --symbols --output=bin/lwbasic.rom src/lwbasic.s +bin/lwbasic-coco2b.rom: src/lwbasic.s + lwasm --raw --list=src/lwbasic-coco2b.list --symbols --output=bin/lwbasic-coco2b.rom -DCOCO2B=1 src/lwbasic.s +bin/lwbasic-coco3.rom: src/lwbasic.s + lwasm --raw --list=src/lwbasic-coco3.list --symbols --output=bin/lwbasic-coco3.rom -DCOCO3=1 src/lwbasic.s + +.PHONY: clean +clean: + rm -f bin/*.rom bin/*.zip + rm -f src/*.list + rm -f */*~ *~ + +bin/coco2.zip: bin/lwbasic.rom + mkdir -p coco2 + rm -f coco2/* coco2.zip + dd if=bin/lwbasic.rom of=coco2/extbas11.rom bs=1024 count=8 + dd if=bin/lwbasic.rom of=coco2/bas12.rom bs=1024 count=8 skip=8 + dd if=bin/lwbasic.rom of=coco2/disk11.rom bs=1024 count=16 skip=16 + zip bin/coco2.zip coco2/extbas11.rom coco2/bas12.rom coco2/disk11.rom + rm -rf coco2 + +bin/coco2b.zip: bin/lwbasic-coco2b.rom + mkdir -p coco2b + rm -f coco2b/* coco2b.zip + dd if=bin/lwbasic-coco2b.rom of=coco2b/extbas11.rom bs=1024 count=8 + dd if=bin/lwbasic-coco2b.rom of=coco2b/bas13.rom bs=1024 count=8 skip=8 + dd if=bin/lwbasic-coco2b.rom of=coco2b/disk11.rom bs=1024 count=16 skip=16 + zip bin/coco2b.zip coco2b/extbas11.rom coco2b/bas13.rom coco2b/disk11.rom + rm -rf coco2b + +bin/coco3.zip: bin/lwbasic-coco3.rom + mkdir -p coco3 + rm -f coco3/* coco3.zip + dd if=bin/lwbasic-coco3.rom of=coco3/coco3.rom bs=1024 count=32 + dd if=/dev/null of=coco3/disk11.rom bs=1024 count=8 + zip bin/coco3.zip coco3/coco3.rom coco3/disk11.rom + rm -rf coco3 + +.PHONY: mame2 +mame2: bin/coco2.zip + mame coco2 -skip_gameinfo -rompath ./bin +mame2d: bin/coco2.zip + mame coco2 -skip_gameinfo -rompath ./bin -debug
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/lwbasic.s Thu Nov 03 21:18:51 2022 -0600 @@ -0,0 +1,147 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; LWBasic Version 0.1 +; Copyright © 2022 Lost Wizard Enterprises Incorporated +; +; This is LWBasic, a replacement Basic ROM system for the TRS-80 Color Computer which +; is most definitely not binary compatible with the stock ROMs. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + *pragmapush list + *pragma nolist + *pragma noexpandcond + *pragmapop list +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Hardware definitions for the I/O page + org 0xff00 +PIA0 equ * ; Keyboard PIA +PIA0.DA rmb 1 ; PIA0 data/direction A +PIA0.CA rmb 1 ; PIA0 control A +PIA0.DB rmb 1 ; PIA0 data/direction B +PIA0.CB rmb 1 ; PIA0 control B + rmb 28 ; mirror images of PIA0 +PIA1 equ * ; DA/misc stuff +PIA1.DA rmb 1 ; PIA1 data/direction A +PIA1.CA rmb 1 ; PIA1 control A +PIA1.DB rmb 1 ; PIA1 data/direction B +PIA1.CB rmb 1 ; PIA1 control B + rmb 28 ; mirror images of PIA1 + rmb 16 ; SCS/Disk controller + rmb 16 ; second half of SCS area + rmb 32 ; miscelaneous hardware + rmb 64 ; unused on Coco 1/2 (GIME on Coco 3) +SAMREG equ * ; the SAM configuration register +SAM.V0CLR rmb 1 ; SAM video mode bits +SAM.V0SET rmb 1 +SAM.V1CLR rmb 1 +SAM.V1SET rmb 1 +SAM.V2CLR rmb 1 +SAM.V2SET rmb 1 +SAM.F0CLR rmb 1 ; SAM screen address bits +SAM.F0SET rmb 1 +SAM.F1CLR rmb 1 +SAM.F1SET rmb 1 +SAM.F2CLR rmb 1 +SAM.F2SET rmb 1 +SAM.F3CLR rmb 1 +SAM.F3SET rmb 1 +SAM.F4CLR rmb 1 +SAM.F4SET rmb 1 +SAM.F5CLR rmb 1 +SAM.F5SET rmb 1 +SAM.F6CLR rmb 1 +SAM.F6SET rmb 1 +SAM.P1CLR rmb 1 ; SAM "page 1" selection (or extra memory type flag) +SAM.P1SET rmb 1 +SAM.R0CLR rmb 1 ; SAM R0 bit (address dependent speedup) +SAM.R0SET rmb 1 +SAM.R1CLR rmb 1 ; SAM R1 bit (full speedup/coco 3 speedup) +SAM.R1SET rmb 1 +SAM.M0CLR rmb 1 ; SAM M0/M1 bits (memory type) +SAM.M0SET rmb 1 +SAM.M1CLR rmb 1 +SAM.M1SET rmb 1 +SAM.TYCLR rmb 1 ; force ROM mode (map type 0) +SAM.TYSET rmb 1 ; set RAM mode (map type 1) + rmb 18 ; *MPU reserved* +CPU.SWI3 rmb 2 ; CPU SWI3 vector +CPU.SWI2 rmb 2 ; CPU SWI2 vector +CPU.FIRQ rmb 2 ; CPU FIRQ vector +CPU.IRQ rmb 2 ; CPU IRQ vector +CPU.SWI rmb 2 ; CPU SWI vector +CPU.NMI rmb 2 ; CPU NMI vector +CPU.RESET rmb 2 ; CPU RESET/startup vector +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Start of memory which has the direct page and other data. + org 0 + rmb 0x100 ; make sure the stuff that isn't direct page is outside of it + rmb 0x100 ; non direct page stuff +textscreen rmb 0x200 ; the actual text screen + + + org 0x8000 ; the hardware puts the ROMs here; it's not negotiable +START clr PIA0.CA ; set PIA0 A to direction mode + clr PIA0.CB ; set PIA0 B to direction mode + clr PIA0.DA ; set PIA0 A to all inputs (comparator, keyboard rows) + ldd #0xff34 ; initiazer for later + sta PIA0.DB ; set PIA0 B to all outputs (keyboard columns) + stb PIA0.CA ; set PIA0 A to data mode, interrupt disabled, MUX to source 0 + stb PIA0.CB ; set PIA0 B to data mode, interrupt disabled, MUX to source 0 + clr PIA1.CA ; set PIA1 A to direction mode + clr PIA1.CB ; set PIA1 B to direction mode + deca ; set PIA1 A bits 7-1 output (DAC, RS232), 0 input (cassette) + sta PIA1.DA + lda #0xf8 ;* set PIA1 B bits 7-3 output (VDG stuff), 2-0 input (single bit sound, + sta PIA1.DB ;* RS232 input, ram size input) + stb PIA1.CA ; set PIA1 A to data mode, interrupt disabled, cassette motor off + stb PIA1.CB ; set PIA1 B to data mode, interrupt disabled, sound off + lda #2 ; set RS232 output to "marking" (stop bit) + sta PIA1.DA + lda #16 ; clear 16 SAM register bits + ldu #SAMREG ; point to SAM register bits +init0 sta ,u++ ; clear SAM bit + decb ; done all? + bne init0 ; brif not +; set the SAM to point to the text screen, which the code will handle at any +; arbitrary 512 byte aligned address in memory + ifne (textscreen)&0x200 + sta (SAM.F0SET-SAMREG)-16,u + endc + ifne (textscreen)&0x400 + sta (SAM.F1SET-SAMREG)-16,u + endc + ifne (textscreen)&0x800 + sta (SAM.F2SET-SAMREG)-16,u + endc + ifne (textscreen)&0x1000 + sta (SAM.F3SET-SAMREG)-16,u + endc + ifne (textscreen)&0x2000 + sta (SAM.F4SET-SAMREG)-16,u + endc + ifne (textscreen)&0x4000 + sta (SAM.F5SET-SAMREG)-16,u + endc + ifne (textscreen)&0x8000 + sta (SAM.F6SET-SAMREG)-16,u + endc + tfr b,dp ; set DP to bottom of memory (B is zero from above) + ldb #4 ; mask for ram size check + sta PIA0.DB ; set RAM size output for probe + bitb PIA1.DB ; is the bit set on ram size input? + beq init2 ; brif not - 4Kx1 RAMs + clr PIA0.DB ; clear RAM size output to see what happens + bitb PIA1.DB ; is it set now? + beq init1 ; brif not - 64Kx1 RAMs + leau -2,u ; adjust pointer so we set the other RAM size bit for the SAM (16Kx1) +init1 sta -3,u ; set M0 (16Kx1) or M1 (64Kx1) +init2 lds #textscreen ; put the stack just below the text screen +; Need to ensure the vectors are at 0xbff2 + zmb 0xbff2-* ; pad ROM up to the vector point + fdb 0 ; SWI3 vector + fdb 0 ; SWI2 vector + fdb 0 ; FIRQ vector + fdb 0 ; IRQ vector + fdb 0 ; SWI vector + fdb 0 ; NMI vector + fdb START ; RESET vector (ROM entry point) +; pad rom to full size + zmb 0x10000-*